/*
	comp8to20.v
	Combine 8 bits input data to 20 bits address
	
	This project and file(s) are released under GNU GPL v3.
	Please find license file from root directory.
	Meng Sun (c) 2013 <leon.meng.sun@gmail.com>
*/

module comp8to20 (Di, CLK, nRESET, LEN, Do);

input [7:0] Di;
input CLK, nRESET, LEN;
output [19:0] Do;

wire [7:0] Di;
wire CLK, nRESET, LEN;
reg [19:0] Do;
reg [7:0] bufDo [2:0];

parameter LatchByte1Done = 0, LatchByte2Done = 1, LatchIdle = 5;
reg [2:0] LatchStatus;

always @ (posedge CLK or negedge nRESET)
begin
	if (nRESET == 0) /*Async-reset*/
	begin
		Do = 20'b0;
		LatchStatus = LatchIdle;
	end else if (LEN == 1)/*Latch enabled*/
	begin
		case (LatchStatus)
		LatchIdle: begin
			bufDo[0] = Di;
			LatchStatus = LatchByte1Done;
			Do = 20'bx;
		end
		LatchByte1Done: begin
			bufDo[1] = Di;
			LatchStatus = LatchByte2Done;
			Do = 20'bx;
		end
		LatchByte2Done: begin
			bufDo[2] = Di;
			Do = {bufDo[2][3], bufDo[2][2], bufDo[2][1], bufDo[2][0], bufDo[1], bufDo[0]};
			LatchStatus = LatchIdle;
		end
		endcase
	end
end

endmodule